This invention relates to an input protection device for a C-MOS device, particularly a C-MOS device based on a silicon gate process.
The C-MOS device usually has an input protection device, which is provided for the purpose of preventing rupture of an MOS FET due to application of a surge voltage to a gate thereof. FIG. 1 is a circuit diagram showing an input protection device. An external input terminal 10 is connected to an input terminal (i.e., gate) of a C-MOS device 14 through an input protection resistor 12. The input terminal of the C-MOS device 14 is also connected to a cathode of a diode 18 through a resistor 16. An anode of the diode 18 is grounded through a resistor 20. When a surge voltage is applied to the input terminal 10 of this structure, the diode 18 is reverse biased, so that the surge voltage is applied between the input terminal 10 and the ground terminal through the resistors 16 and 20 and diode 18 and not applied to the C-MOS device 14. The resistors 16 and 20 are ON resistances of the diode 18 when it is reverse biased.
FIG. 2 is a sectional view showing the structure of the conventional input protection device of the type noted. A p-type well region 24 is formed in the surface region of an n-type semiconductor substrate 22. An n.sup.+ -type layer 26 is formed in the surface region of the p-type well region 24. The layer 26 serves as the cathode of the protection diode 18. Although not shown, p.sup.+ -type layers which serve as the source and drain of a p-channel MOSFET is formed in the surface region of the semiconductor substrate 22, and n.sup.+ -type layers serving as the source and drain of an n-channel MOSFET is formed in the surface region of the p-type well region 24. A field oxide film 28 is formed on the substrate surface, and an n.sup.+ -type polysilicon layer 30 serving as the protection resistor 12 is formed on the field oxide film 28. A CVD oxide film 32 is formed on the polysilicon layer 30. The CVD oxide film 32 has contact holes formed near its opposite ends, and one end of aluminum leads 34 and 36 are connected to opposite end portions of the n.sup.+ -type polysilicon layer 30 through the contact holes. The other end of the aluminum lead 34 is connected to the external input terminal 10. The other end of the aluminum lead 36 is connected to the n.sup.+ -type layer 26 (i.e., the cathode of the diode 18).
The n.sup.+ -type polysilicon layer 30 shown in FIG. 2 constitutes the input protection resistor 12 shown in FIG. 1. Its resistance is currently 1.0 to 1.5 k.OMEGA.. The contact resistance between the aluminum lead 36 and n.sup.+ -layer 26 and the diffusion resistance of the n.sup.+ -layer 26 in FIG. 2 constitute the resistor 16 shown in FIG. 1. Contact resistance between n+-type layer 26 and p-type well 24 and diffusion resistance of p-type well 24 in FIG. 2 constitute the resistor 20 shown in FIG. 1. The gate voltage V.sub.G applied to the input terminal of the CMOS device 14 is given as ##EQU1## where Ra, Rb and Rc represent the resistances of the resistors 12, 16 and 20 respectively and V represents the surge voltage (positive voltage).
It will be seen from the equation (1) that if the resistance Ra of the input protection resistor 12 is much higher than the ON resistances Rb and Rc of the protection diode 18 when the diode is reverse biased, the gate voltage V.sub.G is much lower compared to the surge voltage V. With the structure of FIG. 2, however, the n-type impurity concentration of the n.sup.+ -type layer 26 constituting the cathode of the diode fluctuates greatly. In addition, the contact resistance between the aluminum lead 36 and n.sup.+ -type layer 26 is high, so that the ON resistance Rb +Rc of the diode 18 when it is reverse biased (particularly resistance Rb) is high (usually 490.OMEGA.) and fluctuates greatly.
Meanwhile, there is a trend toward thinner gate oxide films of the C-MOS device together with increasing integration density. This means more stringent demands for the performance of the input protection device. It is desired that the protective breakdown voltage be higher and subject to fewer fluctuations. It may be thought from the equation (1) that the protective breakdown voltage can be increased by increasing the resistance of the input protection resistor. Doing so, however, reduces the operating speed and is undesirable.